As the electronic industry continues to boom, the trend in the development of electronic products is heading in the direction of small size but with high performance, high functionality and high speed. In order to satisfy the requirements of high integration and miniaturization for semiconductor devices, a circuit board provided with a plurality of active/passive components and circuits is developed from a double-layer structure to a multi-layer circuit board. This is achieved by employing the interlayer connection technique to enlarge the usable area of a circuit board with limited space, so that integrated circuits of high wiring density can be incorporated to meet the development trend of miniaturization, high capacity, and high speed of the electronic products.
The circuit board manufacturing industry is ceaselessly pursuing the goals of low cost, high reliability, and high circuit density. To achieve the goals, the industry has developed a “build-up” technique; this technique stacks multiple dielectric layers and circuit layers on the surface of a core circuit board, and forms conductive vias or plated through holes (PTHs) in the dielectric layers to electrically connect the circuit layers. During a circuit build-up process, unbalanced thermal stresses resulted form the difference of the CTEs (coefficient of thermal expansion) can lead to warpage. Generally, to prevent the above problems, a build-up process is performed on both the top and bottom surfaces of the core board, such that a symmetrical built-up structure is formed to prevent warpage.
Given a big difference among CTEs of the conductive traces made of metal, insulating layer, and solder mask layer, warpage occurs to the substrate as a result of a temperature change. Besides, the circuit layouts of the top and bottom surfaces of the core board differ from each other in general, depending on the desired functions. Therefore, different thermal stresses result from the circuit density difference between the circuit layers of the top and bottom surfaces of the core board while temperature changes in fabricating processes such as baking, encapsulant curing, and heat laminating. As a result, unbalanced stresses can lead to warpage, and even lead to delamination.
Furthermore, owing to the blooming development of various portable devices in the field of communication, networking and computing, there have been provided different types of packages such as ball grid array (BGA) package, flip chip package, chip size package (CSP), and multi-chip module (MCM), which are characterized with high density and multiple leads, and have become mainstream products on the semiconductor market. Further, a core structure with semiconductor chip embedded therein has been developed.
FIGS. 1A to 1E are schematic flow charts showing the stepwise processes for embedding a semiconductor chip within a core board structure using prior-art.
Referring to FIG. 1A, a core board 11 having a first surface 11a and an opposite second surface 11b and having a through cavity 110 penetrating the first and the second surface 11a, 11b is provided. A release film 12 is formed on the second surface 11b of the core board 11 to seal one terminal of the through cavity 110.
Referring to FIG. 1B, a semiconductor chip 13 is mounted within the through cavity 110 of the core board 11, wherein the semiconductor chip 13 having an active surface 13a and an opposite inactive surface 13b. The active surface 13a has a plurality of electrode pads 131. The semiconductor chip 13 is mounted on the surface of the release film 12 within the through cavity 110 via the inactive surface 13b. 
Referring to FIG. 1C, an adhesive material 14 fills the gap between the through cavity 110 of the core board 11 and the semiconductor chip 13 to fix the semiconductor chip 13 in the through cavity 110.
Referring to FIG. 1D, the release film 12 is removed.
Referring to FIG. 1E, a built-up structure 15 is formed on the first surface 11a of the core board 11 and the active surface 13a of the semiconductor chip 13, wherein the built-up structure 15 comprising a dielectric layer 151, a circuit layer 152 stacked on the dielectric layer 151, and a plurality of conductive vias 153 formed in the dielectric layer 151. The conductive vias 153 electrically connect to the electrode pads 131 of the semiconductor chip 13. The outmost circuit layer 152 further comprises a plurality of conductive pads 154. Further, a solder mask layer 16 is formed on the outer surface of the built-up structure 15, wherein the solder mask layer 16 has a plurality of openings 160, to thereby expose the conductive pads 154.
Accordingly, to meet the demand of the circuit design, the built-up structure 15 is formed merely on the first surface 11a of the core board 11, so that unbalanced stresses between the opposite surfaces of the package structure can lead to warpage or delamination during fabricating process, and affect the reliability and quality consequentially. Furthermore, the number of laminated layers of the built-up structure 15 is limited by the warpage problem, and accordingly hinder the development of high integration and miniaturization for semiconductor package.
Therefore, there exists a strong need in the art for a circuit board structure to overcome the drawbacks of poor anti-bending strength of the foregoing conventional circuit board structure.